J.-W. Jang, J. Oh, S.-H. Cho, J.-Y. Hong, M. Imran, J. Chung and J.-S. Yang, "Variation Resilient Schemes and Approximation-Free Offset Compensation for Reliable ReRAM-based DNN Accelerators", IEEE Transactions on Emerging Topics in Computing, 2026

S. Kim, J. Moon, J. Oh, I. Choi and J.-S. Yang, "Survey and Evaluation of Converging Architecture in LLMs based on Footsteps of Operations", IEEE Open Journal of the Computer Society, 2025 

P. Pham, T.-M. Park, S.-H. Cho, T. Mahmood, J.-S. Yang, and J. Chung, "AGD: Analytic Gradient Descent for Discrete Optimization in EDA and its Use to Gate Sizing",  ACM Transactions on Design Automation of Electronic Systems, 2025 

J.-Y. Hong, J.-W. Jang, S.-H. Cho, Y. Kong, S. Kim, Y. Kang, J. Ko, J. Chung and J.-S. Yang, "Reducing Errors and Powers in LPDDR for DNN Inference: A Compression and IECC-Based Approach", Journal of Systems Architecture, 2025

T. H. Nguyen, M. Imran, J. Choi and J.-S. Yang, “HYDRA: A Hybrid Resistance Drift Resilient Architecture for Phase Change Memory-Based Neural Network Accelerators,” IEEE Transactions on Computers, 2023

T. H. Nguyen, M. Imran, J. Choi and J.-S. Yang, “CRAFT: Criticality-Aware Fault-Tolerance Enhancement Techniques for Emerging Memories-Based Deep Neural Networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023 [Link] 

H. Kal, H. Choi, I. Jeong,  J.-S. Yang, and W. Ro,  “A convertible neural processor supporting adaptive quantization for real-time neural networks,” Journal of Systems Architecture, 2023

B. Nguyen, J. Choi, and J.-S. Yang, “EUNNet: Efficient UN-normalized Convolution layer for stable training of Deep Residual Networks without Batch Normalization layer,” IEEE ACCESS, 2023

B. Nguyen, J. Choi, and J.-S. Yang, “Checkerboard Dropout: A structured dropout with checkerboard pattern for Convolutional Neural Networks,” IEEE ACCESS, 2022 

M. Imran, T. Kwon, N. Touba and J.-S. Yang, “CEnT: An Efficient Architecture to Eliminate Intra-array Write Disturbance in PCM,” IEEE Transactions on Computers, 2022

M. Imran, T. Kwon, and J.-S. Yang, “ADAPT: A Write Disturbance Aware Programming Technique for Scaled Phase Change Memory,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022

T. Kwon, M. Imran, and J.-S. Yang, “Reliability Enhanced Heterogeneous Phase Change Memory Architecture for Performance and Energy Efficiency,” IEEE Transactions on Computers, 2021

T. Kwon, M. Imran, and J.-S. Yang, “Cost-effective Reliable MLC PCM Architecture Using Virtual Data Based Error Correction,” IEEE ACCESS, 2020 [Link]

T. Kwon, M. Imran, David Z. Pan and J.-S. Yang, “Virtual Tile Based Flip-flop Alignment Methodology for Clock Network Power Optimization,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020 [Link]

I. Ullah, J.-S. Yang, and J. Chung, “ER-TCAM: A Soft-Error Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020 [Link]

M. Imran, H. Han, J. H. Kim, T. Kwon,  J. Chung and J.-S. Yang, “Virtualization Based Efficient TSV Repair for 3-D Integrated Circuits,” IEEE ACCESS, 2019 [Link]

T. Kwon, M. Imran, and J.-S. Yang, “Pattern-Aware Encoding for MLC PCM Storage Density, Energy Efficiency and Performance Enhancement,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019 [Link]

J. Chung, T. Shin, and J.-S. Yang, “Simplifying Deep Neural Networks for FPGA-like Neuromorphic Systems,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018 [Link]

Y. Kang, J. Chung, and J.-S. Yang, “Weight Partitioning for Dynamic Fixed-Point Neuromorphic Computing Systems,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018 [Link]

S.-E. Kim, J. Chung, and J.-S. Yang, “Mitigating Observability Loss of Toggle-based X-Masking via Scan Chain Partitioning,” IEEE Transactions on Computers, 2018 [Link]

C.-H. Oh, S.-E. Kim, and J.-S. Yang, “BIRA With Optimal Repair Rate Using Fault-Free Memory Region for Area Reduction,” IEEE Transactions on Circuits and Systems I, 2017 [Link]

H. Han, J. Chung, and J.-S. Yang, “READ:Reliability Enhancement in 3D-Memory Exploiting Asymmetric SER Distribution,” IEEE Transactions on Computers, 2017 [Link]

T. Lee, D.Z. Pan, and J.-S. Yang, “Clock Network Optimization with Multi-bit Flip-flop Generation Considering Multi-corner Multi-mode Timing Constraint,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017 [Link]

T. Lee, N.A. Touba, and J.-S. Yang, “Enhancing Test Compression with Dependency Analysis for Multiple Expansion Ratios,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016 [Link]

M. Kang, J.-S. Yang, and I.K. Chang, “Studying Trapped Tunneling-Electron Migration due to Program and Erase Cycles in NAND Flash,” IEEE Electron Device Letters, 2016 [Link]

H. Han, N.A. Touba, and J.-S. Yang, “Exploiting Unused Spare Columns and Replaced Columns to Enhance Memory ECC,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015 [Link]

J.-S. Yang, J. Chung and N.A. Touba, “Enhancing Superset X-Canceling Method with Relaxed Constraints on Fault Observation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015 [Link]

T. H. Lee, I. J. Chang, C. Lee, and J.-S. Yang, “Physical Aware Approaches for Speeding up Scan Shift Operation in SoC,” ETRI Journal, 2015 [Link]

J.-Y. Chang, Y. Kim and J.-S. Yang, "3D Probe : Low-cost Variation Modeling Using Inter-test-item Correlations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2014 [Link]

J.-S. Yang, J. Lee and N.A. Touba, “Utilizing ATE Vector Repeat With Linear Decompressor For Test Vector Compression,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2014 [Link]

J.-S. Yang, and N.A. Touba, “Test Point Insertion with Control Point by Greater Use of Existing Functional Flip-Flops,” ETRI Journal, 2014 [Link]

J.-S. Yang, T.H. Han, D. Kobla and E. L. Ju, “Dynamic Self Repair Architectures for Defective Through Silicon Vias,” ETRI Journal, 2014 [Link]

J. Kim, J.-H. Huh, S.-Y. Kim, S.W. Kim and J.-S. Yang, "Low-Power Shared Memory Architecture Power Mode for Mobile System-on-Chip,” IEICE Electronics Express, 2014

C.-L. Li, J.H. Lee, J.-S Yang and T.H. Han, “Communication-aware custom topology generation for VFI network-on-chip,” IEICE Electronics Express, 2014

J.-S. Yang and I.K. Chang, “Robust Buffered Clock Tree Synthesis by Sensitivity Based Link Insertion,” IEICE Transactions on Electronics, Vol. 96, No. 1, pp. 127-131, 2013.

I.K. Chang and J.-S. Yang, “Bit-error Rate Improvement of TLC NAND Flash using State Re-ordering,” IEICE Electronics Express, Vol. 9, No. 23, pp. 1775-1779, 2013.

J.-S. Yang and N.A. Touba, “Improved Trace Buffer Observation via Selective Data Capture Using 2-D Compaction for Post-Silicon Debug,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 21, No. 12, pp. 320-328, 2013 [Link]

J.-S. Yang and N.A. Touba, “Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops,” IEEE Transactions on Computers, Vol. 61, No. 10, pp. 1473-1483, 2012 [Link]

J.-S. Yang and N.A. Touba, “X-Canceling MISR Architectures for Output Response Compaction with Unknown Values,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. 9, pp. 1417-1427, 2012 [Link]

J.-S. Yang and N.A. Touba, “Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 31, No. 3, pp. 442-446, 2012 [Link]