S.-H.Cho, T.-M. Park, J.-Y. Lee, J.-Y. Hong, A. Gerstlauer, and J.-S. Yang, "Explainable GNN-driven Test Point Insertion on Uncontrollable I/Os", Design, Automation and Test in Europe Conference and Exhibition (DATE) , 2026

J.-W. Jang, J. Oh, Y. Kong, J.-Y. Hong, S.-H. Cho, J. Lee, H. Yang, and J.-S. Yang, "Accelerating Retrieval Augmented Language Model via PIM and PNM Integration", IEEE/ACM International Symposium on Microarchitecture (MICRO), 2025

H. Lee and J.-S. Yang, "Self-Error Detection and Correction Techniques for Reliable and Efficient Selector-Only Memory", IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2025

I. Choi, and J.-S. Yang, "DBC: Drift-aware Binary Code for Drift-tolerant Deep Neural Networks", ACM/IEEE Design Automation Conference (DAC), 2025 

I. Choi, Y.-S. Yoon and  J.-S. Yang, "Bit-slice Architecture for DNN Acceleration with Slice-level Sparsity Enhancement and Exploitation", IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2025 

J. -Y. Hong, S. Kim, J.-W. Jang and  J.-S. Yang, "LOCo: LPDDR Optimization with Compression and IECC scheme for DNN Inference", IEEE International Symposium on Low-Power Electronics and Design (ISLPED), 2024 (Received Best Paper Award)

D.-J. Shin, I. Choi, and J.-S. Yang, "ViT-slice: End-to-end Vision Transformer Accelerator with Bit-slice Algorithm", ACM/IEEE Design Automation Conference (DAC), 2024

J.-W. Jang, T. H. Nguyen, and J.-S. Yang, "VECOM: Variation-Resilient Encoding and Offset Compensation Schemes for Reliable ReRAM-Based DNN Accelerator",  ACM/IEEE International Conference On Computer Aided Design (ICCAD),  2023

I. Choi, J.-Y. Hong, J. Jeon, and J.-S. Yang, “RQ-DNN: Reliable Quantization for Fault-tolerant Deep Neural Network,” ACM/IEEE Design Automation Conference Late Breaking Results (DAC), 2023

J. Jeon, J.-Y. Hong, S. Kim, I. Choi, and J.-S. Yang, “PIE-DRAM: Postponing IECC to Enhance DRAM performance with access table,” ACM/IEEE Design Automation Conference Late Breaking Results (DAC), 2023

T. H. Nguyen, M. Imran, and J.-S. Yang, “DynaPAT: A Dynamic Pattern-Aware Encoding Technique for Robust MLC PCM-Based Deep Neural Networks,” ACM/IEEE International Conference On Computer Aided Design (ICCAD), 2022

S.-Y. Lee, I. Choi and J.-S. Yang, “Bipolar Vector Classifier for Fault-tolerant Deep Neural Networks,” Proc. of ACM/IEEE Design Automation Conference (DAC), 2022

S.-S. Lee, and J.-S. Yang, “Value-aware Parity Insertion ECC for Fault-tolerant Deep Neural Network,” Proc. of ACM/IEEE Design, Automation & Test in Europe (DATE), 2022

T. H. Nguyen, M. Imran, J. Choi, and J.-S. Yang, "Low-Cost and Effective Fault-Tolerance Enhancement Techniques for Emerging Memories-Based Deep Neural Networks,” Proc. of ACM/IEEE Design Automation Conference (DAC), 2021

S. Jeong, S. Y. Kang, and J.-S. Yang, "PAIR: Pin-aligned In-DRAM ECC architecture using expandability of Reed-Solomon code,” Proc. of ACM/IEEE Design Automation Conference (DAC), 2020 (Nominated for Best Paper Candidate)

I. Ullah, K. Inayat, J.-S. Yang and J. Chung, "Factored Radix-8 Systolic Array for Tensor Processing,” Proc. of ACM/IEEE Design Automation Conference (DAC), 2020

M. Imran, T. Kwon,  and J.-S. Yang, “Effective Write Disturbance Mitigation Encoding Scheme for High-density PCM,” Proc. of ACM/IEEE Design, Automation & Test in Europe (DATE), 2020

J.-H. Kim, H.-J. Jo, K.-K. Jo, S. Cho, J. Chung, and J.-S. Yang, “Reliable and Lightweight PUF-based Key Generation using Various Index Voting Architecture,” Proc. of ACM/IEEE Design, Automation & Test in Europe (DATE), 2020

M. Imran, T. Kwon, J. M. You, and J.-S. Yang, “Flipcy: Efficient Pattern Redistribution for Enhancing MLC PCM Reliability and Storage Density,” ACM/IEEE International Conference On Computer Aided Design (ICCAD), 2019 [Link]

Y. M. Lee, and J.-S. Yang, “WiP : Computation offloading of acoustic model for client-edge-based speech recognition,” International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), 2019 [Link]

J. Kim, and  J.-S. Yang, "DRIS-3: Deep Neural Network Reliability Improvement Scheme in 3D Die-Stacked Memory based on Fault Analysis,” Proc. of ACM/IEEE Design Automation Conference (DAC), 2019 [Link]

J. M. You, and  J.-S. Yang, "MRLoc: Mitigating Row-hammering based on memory Locality,” Proc. of ACM/IEEE Design Automation Conference (DAC), 2019 [Link]

B. Seo, and J.-S. Yang, “Power Optimization for Emerging NVM-based NVMe SSD through Self Performance Training,” ACM/IEEE Design Automation Conference (DAC), Work-In-Progress Session, 2019  

M. Imran, T. Kwon, J. M. You, and J.-S. Yang, “Flipcy: Efficient Pattern Redistribution for Enhancing MLC PCM Reliability and Storage Density,” ACM/IEEE Design Automation Conference (DAC), Work-In-Progress Session, 2019

S. Jeong, and J.-S. Yang, “PETS: Pin Level Error Checking and Correcting Architecture of DRAM with Toggling Sense Amplifier,” ACM/IEEE Design Automation Conference (DAC), Work-In-Progress Session, 2019

S. Kim, and J.-S. Yang, “Optimized I/O Determinism for Emerging NVM-based NVMe SSD in an Enterprise System”, Proc. of ACM/IEEE Design Automation Conference (DAC), 2018 [Link]

H. Chae, and J.-S. Yang, “Test Cost Reduction for X-Value Elimination By Scan Slice Correlation Analysis”, Proc. of ACM/IEEE Design Automation Conference (DAC), 2018 [Link]

B. S. Kim, and J.-S. Yang, “Bayesian Theory based Switching Probability Calculation Method of Critical Timing Path for On-chip Timing Slack Monitoring," Proc. of ACM/IEEE Design, Automation & Test in Europe (DATE), 2018 [Link]

T. Kwon, M. Imran, J. M. You and J.-S. Yang, “Heterogeneous PCM array architecture for reliability, performance and lifetime enhancement," Proc. of ACM/IEEE Design, Automation & Test in Europe (DATE), 2018 [Link]

B. S. Kim, and J.-S. Yang, “System Level Performance Analysis and Optimization for The Adaptive Clocking based Multi-Core Processor," IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), 2018 [Link]

S. Kim, and J.-S. Yang, “WiP: Improving NVMe SSD I/O Determinism with PCIe Virtual Channel," International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), 2017

Y. Kim, and J.-S. Yang, “High Speed and Power Efficient Hierarchical SEC-DAEC-DEC code for Reliable Memory," ACM/IEEE Design Automation Conference (DAC), Work-In-Progress Session, 2017  

B. S. Kim, H. S. Won, and J.-S. Yang, “Observability Probability of Timing Critical Path Aware On-Chip Performance Monitoring Methodology," ACM/IEEE Design Automation Conference (DAC), Work-In-Progress Session, 2017  

B. S. Kim, H. S. Won, T. H. Han, and J.-S. Yang, “Non-linear Library Characterization Method for FinFET Logic Cells by L1-minimization," Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), 2017  

S.-Y. Park, S. Lim, D. Jeong, J. Lee,  J.-S. Yang and H. Lee , “PUFSec: Device Fingerprint-based Security Architecture for Internet of Things," Proc. of IEEE International Conference on Computer Communications (INFOCOM), 2017 [Link]

S. Lee, and J.-S. Yang, “MVP ECC : Manufacturing process Variation aware unequal Protection ECC for memory reliability," Proc. of ACM/IEEE Design, Automation & Test in Europe (DATE), 2017 [Link]

J. Kang, N.A. Touba, and J.-S. Yang, “Reducing Output Response Compaction Overhead by Exploiting X-Value Correlation,” Proc. of ACM/IEEE Design Automation Conference (DAC), 2016 [Link]

Y. Kim, and J.-S. Yang, “Power Efficient Hierarchical SEC-DAEC-DEC code for Reliable Memory,” ACM/IEEE Design Automation Conference (DAC), Work-In-Progress Session, 2016

T. Lee, J. Yi, and J.-S. Yang, “Multi-bit Flip-flop Generation Considering Multi-corner Multi-mode Timing Constraint,” Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), 2016

B. S. Kim, H. S. Won, T. Han, and J.-S. Yang, “AFSEM : Advanced Frequent Subcircuit Extraction Method by graph mining approach for optimized cell library developments,” Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), 2016

H. Han, and J.-S. Yang, “Asymmetric ECC organization in 3D-memory via spare column utilization,” Proc. of IEEE Symposium on Defect and Fault Tolerance, 2015

B.-J. Jang, C.-H. Lee, S.-H. Sim, K.-W. Choi, D.-H. Byun, Y.-H. Jung, K.-M. Park, D.-Y. Heo, G.-H. Kim, and J.-S. Yang, “Robust via-programmable ROM design based on 45nm process considering process variation and enhancement Vmin and yield,” Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), 2015

M.-C. Park, G.-Y. Yang, J.-S. Yang, K.-H. Lee and Y.-K Park, “New Perspective on Lifetime Prediction Approach for BTI and HCI Stressed Device and Its Impact on Circuit Lifetime,” Proc. of International Conference on Simulation of Semiconductor Processes and Devices, 2014

S. Oh, J.-S. Yang, A. Bianchi and H. Kim, “Power Replay Attack in Electronic Door Locks,” IEEE Symposium on Security and Privacy (Poster), 2014

K. Han, J.-S. Yang and J.A. Abraham, “Enhanced Algorithm of Combining Trace and Scan Signals in Post-Silicon Validation,” Proc. of IEEE VLSI Test Symposium, pp. 1-6, 2013. (Nominated for Best Paper Award) [Link]

K. Han, J.-S. Yang and J.A. Abraham, “Dynamic Trace Signal Selection for Post-Silicon Validation,” Proc. of IEEE International Conference on VLSI Design, pp. 302-307, 2013. [Link]

J.-S. Yang and R. Datta, “Efficient Function Mapping in Nanoscale Crossbar Architecture,” Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 190-196, 2011. [Link]

J.-S. Yang, B. Nadeau-Dostie and N.A. Touba, “Test Point Insertion Using Functional Flip-Flops to Drive Control Points,” Proc. of IEEE International Test Conference, pp. 1-10, 2009. [Link]

J.-S. Yang, N.A. Touba, S.Y. Yang and Y.M. Mak, “An Industrial Case Study of X-Canceling MISR,” Proc. of IEEE International Test Conference, pp. 1-10, 2009. [Link]

J.-S. Yang, N.A. Touba and B. Nadeau-Dostie, “Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points,” Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 20-28, 2009. [Link]

J.-S. Yang and N.A. Touba, “Automated Selection of Signals to Observer for Efficient Silicon Debug,” Proc. of IEEE VLSI Test Symposium, pp. 79-84, 2009.  [Link]

J.-S. Yang, and N.A. Touba, “Enhancing Silicon Debug via Periodic Monitoring,” Proc. of IEEE Symposium on Defect and Fault Tolerance, pp. 125-133, 2008.  (Received Best Paper Award) [Link]

J.-S. Yang and N.A. Touba, “Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture,” Proc. of IEEE VLSI Test Symposium, pp. 345-351, 2008. [Link]

J.-S. Yang, A. Rajaram, N. Shi, J. Chen and D.Z. Pan, “Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis,” Proc. of International Symposium on Quality Electronic Design (ISQED), pp. 398-403, 2007. [Link]